OpenVAF is still in development and there are still many goals on the roadmap:

  • Noise analysis (planned for 2023)
  • Reaching full compliance with the Verilog-A standard
    • Behavioral modelling features
    • Support for features that allow defining full circuits/full PDKs in Verilog-A
  • OSDI integration in Xyce
  • Improved documentation
  • A detailed paper about the technical innovations in OpenVAF and attendance at international conferences

We are always looking for cooperation partners, please do not hesitate to contact SemiMod GmbH.